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KSP Inc.

Demand is surging for advanced packages integrating heterogeneous chips for AI and HPC. Stacking materials of differing thermal expansion warps wafers and panels by millimetres, causing handling errors and bonding defects: the bottleneck limiting yield. Conventional correction clamps the substrate between rigid plates and heats it in a furnace for about ten hours, where stress concentration causes breakage. The project develops a warpage-correction machine using a pair of Auxetic-structured Variable-Curvature Electro-Static Chucks (A-VCESC). Conforming to the warped shape, it holds the substrate uniformly over its whole face and flattens it without damage by solid-conduction heating and stepwise stress relief. The target is bow/warp residual under 10 µm, including large rectangular panels.
The core business is the manufacture and sale of the warpage-correction machine. The first product is a standalone unit supplied to back-end equipment makers and assembly subcontractors. Added to this are module sales and patent licensing for in-tool integration, plus simulation and consulting that optimise thermal and pressure histories. Customer data accumulates as proprietary know-how.
FY2026 builds the basic design and a single-unit prototype of a vacuum-compatible A-VCESC, demonstrating chucking, release and planar-to-curved transition. In parallel, at least eight interviews with back-end equipment makers narrow the initial target to one or two process steps and define product requirements. FY2027 brings a large-panel prototype, verification of active curvature control and solid-conduction heating, and a paid PoC or joint-development contract with at least one equipment maker. In FY2028 a product-level prototype achieves a residual under 10 µm and agreement between analysis and measurement within 10 percent, with PoCs extended to several firms. FY2029 completes final verification and in-tool demonstration, leading to a startup and seed funding in October.